Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit

ABSTRACT

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional of, and claims benefit ofpriority under 35 U.S.C. §119(e) from, U.S. Provisional PatentApplication No. 61/887,919, filed Oct. 7, 2013, the entirety of which isexpressly incorporated herein by reference.

BACKGROUND OF THE INVENTION

Superconducting integrated circuits (ICs) based on Josephson junctions(JJs) are capable of operation with very low power and high speed,orders of magnitude beyond those possible using conventionalsemiconducting circuits. Recently, superconducting single flux quantum(SFQ) circuits have progressed to even lower power versions withzero-static power dissipation (Mukhanov, U.S. Pat. No. 8,571,614; Herr,U.S. Pat. No. 7,852,106), making them highly competitive for applicationin next generation energy-efficient computing systems. However, thepractical realization of superconducting digital circuits for high-endcomputing requires a significant increase in circuit complexity and gatedensity. Conventional SFQ integrated circuit fabrication technology hasbeen proven to deliver SFQ digital ICs with more than 10,000 JJs perdie, using a fabrication process with just 4 superconducting niobium(Nb) layers and relatively coarse (1.0 μm) lithography with 1.5-2 μmminimum JJ size, without layer planarization. Further increase inintegration density and scale of superconducting ICs requires finerlithography to reduce the size of all circuit components including JJs,vias, thin-film inductors, thin-film resistors, and interconnects. Notethat this is a different application than superconducting quantumcomputing based on similar JJs, for which the required circuitcomplexity is significantly less, but the operating temperature is muchlower (see, e.g., Ladizinsky, US20110089405).

The biggest gain in the IC integration scale can be achieved by addingmore superconducting layers using layer planarization, which becomesessential to avoid problems associated with lines over edges. Hinode(U.S. Pat. No. 7,081,417) has demonstrated up to 10 Nb layers withsubmicron JJ size using planarization based on chemical mechanicalpolishing (CMP). CMP is generally the rate-limiting step in the overallprocess, and can also lead to contamination, given that it is a wetprocess that may generate particulate residues. Another known problemwith CMP is that the layer planarization rate may depend on the detailedpattern and scale of the devices in a given layer, and may thereforevary within a layer and between layers. One solution to this problem isto incorporate standard dummy patterns in sparsely populated regions(see, e.g., Chen, U.S. Pat. No. 7,235,424). In contrast, Hinodedeveloped a process without such dummy patterns, but using an invertedmask and etching to create a narrow standard “Caldera” (or crater edge)at all edges. Overall, this creates structures that are largelyindependent of pattern and scale, permitting control and uniformity ofthe CMP process.

In order to obtain the greatest increase in circuit density by addingsuperconducting layers, one needs stackable vias (or plugs) allowingconnection between multiple metal layers with minimal parasiticinductance, while not compromising circuit area. This has been adifficult problem requiring the development of special fabricationtechniques (e.g., Tolpygo, U.S. Pat. Nos. 8,301,214; 8,437,818).

In general, any fully planarized process requires one step ofplanarization (using, e.g., CMP) for each patternable layer. Forexample, consider a basic wiring bi-layer such as that shown in FIG.25A, comprising a lower wiring layer and an upper insulating layer. Theinsulating layer must contain holes which are penetrated by conductingvias that can connect the lower wiring layer to other wiring layersabove. A standard planarized process would comprise first patterning themetals and insulators in the bottom wiring layer, followed by a firstplanarization step leading to the intermediate structure in FIG. 25B.This would be followed by depositing and patterning the insulator andmetal in the top insulator/via layer, followed by a second planarizationstep.

The art fails to provide a multi-layer planarization process thatrequires only a single step of chemical mechanical polishing for eachwiring bi-layer.

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Each of the foregoing references and patent documents is expresslyincorporated herein by reference in its entirety.

SUMMARY OF THE INVENTION

The planarized fabrication process technique of the present technologyfeatures pattern-independent interlayer dielectric planarization. Thistechnique allows faster planarization with integrated stackablevia-plugs. Further, it can be combined with legacy non-planarized layersabove a planarized base. It is further referred to as Rapid IntegratedPlanarized Process for Layer Extension (RIPPLE).

FIGS. 14-20 show cross-sections (B) and perspective top views (A) ofvarious stages of the planarized process. For compatibility with theHypres Inc. legacy (non-planarized) 4-layer process, additional wiringlayers are provided underneath the ground plane (layer M0), which wasthe base layer on the wafer in the legacy process. These “underground”layers (Mn1-Mn8 in FIG. 24, where n stands for “negative”) illustratethe extendible nature of RIPPLE.

One embodiment of the process is summarized in FIGS. 14-20, forproviding a single extended superconducting layer. This starts with asputter deposition of a Nb/Al/Nb trilayer (200 nm/10 nm/200 nm filmthicknesses), where the top Nb film is used to define via plugs, thebottom for the wiring layer, and Al in between them as an etch stop. Ofcourse, other superconducting materials and etch stop technologies maybe employed. The first step is the via (In1) plugs definition done byetching the top niobium layer by using SF₆ chemistry with hard etch stopat the Al layer (FIGS. 14A and 14B). Note that this via is in the upperlayer, but is patterned before patterning the wiring in the lower layer,opposite to the standard process.

The next step is removing residual aluminum. This can be accomplished byusing either wet-etch or dry-etch process. A reliable wet etch processuses ion-free metal developer at an etch rate of 5 nm/min, while a dryetch can be done either by inductively coupled plasma reactive ion etch(RIE) in chlorine chemistry, or by ion beam milling. Note that the 10 nmof Al left between the two Nb layers in the via does not degrade thesuperconductivity in the via during circuit operation, since the thin Alis induced into the superconducting state by the Nb on both sides.

The next step is patterning the metallic wires in the lower Nb layer,using pattern Mn1, after the top Nb via has already been defined,completing the reversal of the standard process. There is no planarizedintermediate step of the type shown in FIG. 25B.

The next step is a deposition of a 200 nm interlayer dielectric (SiO₂),done with PECVD (FIGS. 16A and 16B) that conformally covers the entirewafer with a 200 nm thick SiO₂. Then, the wafer is patterned with acomplementary to the metal pattern (Mn1) mask biased by 0.2-μm formisalignment compensation (Mn1c). The mask has been generatedautomatically, omitting smaller than 0.6 μm objects. All SiO₂ on top ofthe metal, except for a narrow (˜0.2 μm) Caldera edge (similar to thatin the Hinode process), is etched away in CHF₃/O₂ RIE chemistry. Theresulting structure is shown in FIGS. 17A and 17B. Then, the secondinterlayer dielectric is deposited on the entire wafer (FIGS. 18A and18B) with its thickness (200 nm) equal to the thickness of the pluglayer (top Nb layer of the trilayer deposited during the first step).

In the next step, a mask, In1c, complementary to via mask In1, is usedto pattern and remove SiO₂ from the top of via plugs (FIGS. 19A and19B). After this stage, the wafer is populated with 200-nm-thick by˜200-nm-wide uniform structures. These pattern-independent structurescan be easily removed from the entire wafer by chemical-mechanicalplanarization. The polishing rate for these structures is 3 times fasterthan the rate for a blanket film. The final planarized layer and aplugged via are shown in FIGS. 20A and 20B. Even though the CMP step isthe only step that doesn't have a direct method of determining theend-point, it has been made reliable by the pattern-independent natureof the technique. Moreover, only one CMP step is needed for defining awiring layer and via plugs.

This sequence can be repeated for any given number of wiring layers,thus producing reliable fabrication process extension. A key advantageof this approach is that it is fully compatible with all designs madefor the legacy 4-layer non-planarized process.

An alternative embodiment of the new process (FIGS. 26A, 26B and 26C)can be achieved without the need for the Al etch-stop layer (and for thesteps corresponding to the removal of residual aluminum). The processstarts with the deposition of 200 nm niobium thin film followed by viaplugs patterning and definition (FIG. 26A). The next step is to deposita 200-nm thick niobium film by sputtering (FIG. 26B). During this step,the via-plugs will get coated conformally and grow together with thewiring layer. At this stage, the wiring layer is patterned and defined;the resulting structure is shown in FIG. 26C. Then 200 nm PECVD SiO₂(the same thickness as the wiring layer) is deposited, yielding the samestructure as shown in FIGS. 16A and 16B, except for the aluminum. Therest of the process follows the RIPPLE steps described with respect toFIGS. 17-20. The other advantage of this process is the elimination ofthe additional complementary mask for the via-plugs (In1c). This ispossible because the plug area has already been enlarged by the neededmisalignment compensation of 200 nm during the deposition of the wiringlayer. As a result, the same mask (In1) can be used with a negativeresist for etching the interlayer dielectric (ILD) inside the via (as inFIGS. 19A and 19B). In this case also, only a single CMP step is neededfor each wiring layer, including the via plug. This alternativeembodiment may provide improved reliability and speed by skipping thealuminum etch step.

These are representative examples of the RIPPLE process, and others arealso possible. The key is to require only a single CMP step for eachwiring bi-layer in a process that can be extended to an arbitrary numberof such bi-layers with small stacked vias between them, that can bescaled to arbitrarily small dimensions, while maintaining thepossibility of non-planarized layers on top.

It is therefore an object to provide a planarized integrated circuit ona substrate, comprising: at least one planarized layer, and preferably aplurality of planarized layers formed successively on the substrate,each respective layer comprising: an electrically conductive layer; anelectrically conductive via layer adjacent to the electricallyconductive layer; wherein the electrically conductive via layer adjacentto the electrically conductive layer is patterned into a set of viaswhich define a set of vertically extending structures which electricallyinterconnect with conductive structures of an adjacent layer, and theelectrically conductive layer is patterned into a set of wires byremoval of the surrounding portions of the electrically conductivelayer, with the set of vertically extending structures extending abovethe set of wires; and a planarized insulating layer formed over the setof wires and the set of vias, such that upper portions of the set ofvertically extending structures are exposed through the planarizedinsulating layer.

It is also an object to provide a method of forming a planarizedintegrated circuit on a substrate, comprising a planarized layer, andpreferably a series of successive planarized layers, comprising: formingan electrically conductive layer; forming an electrically conductive vialayer; patterning the via layer into a set of vias; after patterning theelectrically conductive via layer, patterning the electricallyconductive layer into a set of wires, wherein portions where the set ofvias coincide in a plane of the planarized layer with the set of wiresdefine vertically extending conductive structures configured to providea conductive path between the set of wires of the respective layer and aset of wires of an adjacent layer; forming an insulating layersurrounding the set of wires and the set of vias; and planarizing theinsulating layer such that portions of the vertically extendingstructures are exposed and the set of wires is covered.

The electrically conductive layer may be covered with an etch stoplayer, and the electrically conductive via layer formed over the etchstop layer, the electrically conductive via layer formed over the etchstop layer being patterned into the set of vias exposing the etch stoplayer surrounding the set of vias, and the electrically conductive layeris subsequently patterned into a set of wires by removal of thesurrounding portions of the etch stop layer and electrically conductivelayer, such that portions of the electrically conductive via layer areexposed through the planarized insulating layer.

The electrically conductive layer and the electrically conductive vialayer may each be formed of a cryogenically superconductive material,and the etch stop layer formed of a material susceptible to inducedsuperconductivity by proximity to the cryogenically superconductivematerial at cryogenic temperatures. The etch stop layer may comprisealuminum.

The electrically conductive layer may alternately be formed over the setof vias formed by patterning the electrically conductive via layer, theelectrically conductive layer being patterned into the set of wiressuperposed on the set of vias, such that portions of the set of wireswhich overlie the set of vias form tops of the vertically extendingstructures which are exposed through the planarized insulating layer.

At least one of the electrically conductive layer and the electricallyconductive via layer may comprise a niobium-based superconductivematerial.

The insulating layer may comprise silicon dioxide.

The integrated circuit may further comprise at least one non-planarizedcircuit layer lying above at least one planarized layer.

The integrated circuit may further comprise at least one Josephsonjunction formed within a planarized layer or a non-planarized layerformed on top of the planarized layers, electrically connected to theset of wires.

The integrated circuit may further comprise a single-flux-quantumcircuit formed within a planarized layer or a non-planarized layer,electrically connected to the set of wires.

A minimum transverse dimension of a conductive wire may be less than 1micron.

At least one conductive layer may comprise a ground plane.

At least 10 planarized layers may be present.

The method may further comprise depositing the electrically conductivelayer on a planarized surface of a preceding layer, forming an etch stoplayer on the electrically conductive layer, and forming the electricallyconductive via layer over the etch stop layer, wherein the electricallyconductive via layer is initially patterned to expose the etch stoplayer surrounding the set of vias, and the portions of the etch stoplayer and electrically conductive layer surrounding the set of wires aresubsequently removed, such that the set of vias comprise the verticallyextending structures.

The electrically conductive layer and the electrically conductive vialayer may each be independently formed of a cryogenicallysuperconductive material, and the etch stop layer may be formed of amaterial susceptible to induced superconductivity by proximity to thecryogenically superconductive material at cryogenic temperatures.

The method may further comprise depositing the electrically conductivevia layer on a planarized surface of a preceding layer, patterning theelectrically conductive via layer to form the set of vias, forming theelectrically conductive layer over the formed set of vias, andpatterning the electrically conductive layer formed over the set ofvias, wherein portions of the electrically conductive layer which aresuperposed on the set of vias comprise the vertically extendingstructures.

The planarizing may comprise chemical-mechanical polishing.

The integrated circuit may be formed with a various number of successiveplanarized layers, e.g., 1, or 2, or 3, or 4, or 5, or 6, or 7, or 8, or9, or 10, or 11, or 12, or 13, or 14, or 15, or 16, or more successiveplanarized layers.

At least one of the electrically conductive layer, the electricallyconductive via layer, and an optional etch stop layer formed on theelectrically conductive layer may be deposited using sputtering. Theinsulating layer may be deposited by plasma enhanced chemical vapordeposition. At least one of the electrically conductive layer and theelectrically conductive via layer may be patterned by reactive ionetching.

The method may further comprise creating narrow peaks around edges ofthe insulating layer, to provide a pattern-independent planarization ofthe insulating layer.

The electrically conductive layer and the electrically conductive vialayer may each be formed of a cryogenically superconductive material,optionally separated by a layer which is inducible to superconductivityby proximity to cryogenically superconductive material under cryogenicconditions.

A further object provides a planarized integrated circuit having asubstrate, comprising at least one planarized layer formed on thesubstrate, a respective planarized layer comprising:

at least two layers of cryogenically superconductive material, a wiringlayer patterned to provide lateral conductive pathways in a plane of arespective layer, and a via layer patterned to provide verticallyconductive pathways between adjacent layers, wherein the via layer ispatterned prior to the wiring layer such that a respective via comprisesa stack of the electrically conductive via layer and the electricallyconductive layer to having a height above a surrounding portion of thewiring layer; and

an insulating layer formed over the at least two layers, covering thewiring layer, wherein the insulating layer is planarized to expose anupper portion of the stacks of electrically conductive via layer and theelectrically conductive layer.

The electrically conductive via layer and the electrically conductivelayer may each be formed of a cryogenically superconducting material,having an optional induced superconductivity layer therebetween, theintegrated circuit further comprising a least two Josephson junctionselectrically communicating through at least one wiring layer. TheJosephson junctions may be formed in different layers, or the samelayer, and the layer(s) in which they are formed may be planarized ornon-planarized. For example, the Josephson junctions may be formed on anupper set of layers which are non-planarized, formed over a stable ofplanarized wiring layers, which may include various passive components,such as resistors and inductors, in addition to the set of wires.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a First layer of the Prior Art Hypres Inc. process M0,sputter deposited, dark field mask lithography, SF₆ RIE etched,chemically stripped. Moats and ground pad holes defined;

FIG. 2 shows the Second layer of the Prior Art Hypres Inc. process I0,Ion Beam deposited, dark field mask lithography defining Vias between M1and M0, etched in CH₄+O₂ mixture, chemically stripped;

FIG. 3 shows the Third layer of the Prior Art Hypres Inc. processTri-layer in situ sputter deposited Nb/Al/AlOx/Nb, I1C clear field masklithography defining junctions hard baked photoresist, Anodization,chemically stripped;

FIG. 4 shows the Fourth layer of the Prior Art Hypres Inc. process A1,Anodization ring definition, A1 clear field mask lithography definingJosephson Junctions, Ion Beam milled, chemically stripped;

FIG. 5 shows the fifth layer of the Prior Art Hypres Inc. process M1,base electrode of the tri-layer. M1 clear field mask lithographydefining inductances and interconnects by RIE, chemically stripped;

FIG. 6 shows the sixth layer of the Prior Art Hypres Inc. process R2,Sputter deposited molybdenum, clear field mask lithography defining theshunt and bias resistors of the circuit, SF₆ plasma etched, chemicallystripped;

FIG. 7 shows the seventh layer of the Prior Art Hypres Inc. processI1B-1 and I1B-2, PECVD deposited, I1B lithography dark field maskdefining vias to Junction, resistors and contact pads, etched in CH4+O2mixture, chemically stripped;

FIG. 8 shows the Eighth layer of the Prior Art Hypres Inc. process M2,sputter deposited niobium, clear field mask lithography defining M2inductors and interconnects, SF₆ RIE etched, chemically stripped;

FIG. 9 shows the ninth layer of the Prior Art Hypres Inc. process M2,PECVD deposited, dark field mask lithography defining vias to contactpad and M2 wiring, etched in CH4+O2 mixture, chemically stripped;

FIG. 10 shows the tenth layer of the Prior Art Hypres Inc. process M3,sputter deposited niobium, clear field mask lithography defining M3interconnects, SF₆ RIE etched, chemically stripped;

FIG. 11 shows the eleventh layer of the Prior Art Hypres Inc. processR3, Image reversal lithography using clear field mask defining R3,electron beam evaporated Ti/Pl/Au, Lift-off, chemically cleaned;

FIG. 12 show a layout of a shunted Junction of the Prior Art Hypres Inc.process, connected to bias pad with a bias resistor and grounded throughthe base electrode of the junction;

FIG. 13 shows the base technology level description of the RIPPLE-7process according to the present invention, where Mn8 to M0 layers areplanarized;

FIGS. 14A and 14B show the xth Superconducting metal layer extension,after plug definition;

FIGS. 15A and 15B show the Al wet etch, Pattern #2, Niobium metal RIE;

FIGS. 16A and 16B show the First Interlayer dielectric (SiO₂)deposition;

FIGS. 17A and 17B show the removal of Interlayer dielectric by ReactiveIon Etch;

FIGS. 18A and 18B show the Second ILD deposition;

FIGS. 19A and 19B show the ILD Planarization by RIE SiO₂ etch;

FIGS. 20A and 20B show Chemical Mechanical Planarization;

FIGS. 21A and 21B show an alternative method (using Anodization);

FIG. 22 shows a prior art 4-layer metal process;

FIG. 23 shows a planarized 6 metal layer process;

FIG. 24 shows RIPPLE-8, a process with 12 superconducting layers,Shielded passive transmission lines, shielded DC power distributions;

FIGS. 25A and 25B show schematic planarized layers according to thePrior Art; and

FIGS. 26A, 26B and 26C show via plugs and underground superconductingwire defined without aluminum etch stop; 26A After the definition of thevia-plug; 26B After the deposition of the metal layer; and 26C After thedefinition of the wiring layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

1.0 Prior Art Fabrication Process

The details of a known Hypres Inc. (Elmsford N.Y.) the process flow willbe described by following the cross-section of a biased, shuntedJosephson junction as it made layer-by-layer. The layout of this isgiven in FIG. 12, which shows a layout of a shunted Junction connectedto a bias pad with a bias resistor and grounded through the baseelectrode of the junction.

The process starts with a bare 150 mm diameter oxidized silicon wafer bydeposition the first Nb metal layer (M0). Of course, other substratesmay be used. Typically, the substrate is planarized before the firststep, and indeed, may be a planarized circuit formed from precedingmanufacturing steps.

The deposition is done in a cryo-pumped chamber to a pressure of about10⁻⁷ Torr. Magnetron sputtering is used for deposition, where the waferis scanned under the target at constant speed. Both the scan speed andthe chamber pressure are adjusted to get the required film thicknessgrowing without stress. At 3 kW power the wafer is scanned at 20 cm/secto make a film of thickness 1000 Å for M0 at a stress-free chamberpressure of 17 mTorr. After deposition the Nb thin film is patternedusing the M0-mask, a dark field mask and a positive photoresist AZ5214-EIR. The pattern is transferred to the thin film after etching it inend-point-detected SF₆ plasma RIE. Following etching, the resist andetch by-products are stripped and cleared by wet processing. The finalcross section after the completion of the first layer is given in FIG. 1(The figure is to scale with nano-meter scale on the Y-axis andmicro-meter scale on the X-axis), shows a First layer—M0, sputterdeposited, dark field mask lithography, SF₆ RIE etched, chemicallystripped. Moats and ground pad holes are defined.

The following describes the 11 layers of the standard Hypres Inc.(Elmsford N.Y.) legacy (non-planarized) fabrication process, accordingto a preferred embodiment:

1.1 M0—the First Niobium Superconductor Layer

The first Niobium superconductor layer is grown to a thickness of 1000Å±10% and the film's sheet resistance at room temperature is1.90±0.2Ω/□. In a circuit this layer is used as grounding and most ofthe return current flows through it. To reduce the effect of groundcurrent induced magnetic field interference to the operation of thecircuit, a number of holes and moats are included in this layer. Holesand moats can have a minimum size of 2×2 μm and a bias (0.25±0.25) μmand a minimum spacing of 3 μm between them.

1.2 I0—Interlayer Dielectric Between M0 and M1

FIG. 2 shows the Second layer I0—Ion Beam deposited, dark field masklithography defining Vias between M1 and M0, etched in CH₄+O₂ mixture,chemically stripped.

The interlayer dielectric between M0 and M1 is PECVD deposited SiO₂insulator of thickness 1500 Å±10% with a specific capacitance of 0.277fF/μm²±20%. Contact to M0 is through I0 vias with a minimum size of 2×2μm and a bias (0.30±0.25) μm. The alignment tolerance of I0 to M0 is±0.25 μm.

1.3 I1C—Niobium Superconductor Counter Electrode of the Tri-Layer

FIG. 3 shows the Third layer—Tri-layer in situ sputter depositedNb/Al/AlO_(x)/Nb, I1C clear field mask lithography defining junctionshard baked photoresist, Anodization, chemically stripped.

The Niobium superconductor counter electrode of the tri-layer isdeposited by magnetron sputtering in a load locked, cryo-pumped chamberwith a base pressure of 1×10⁻⁹ T. It is grown to a thickness of 500Å±10%. Junctions are defined in this layer by using a Clearfield maskI1C. The alignment tolerance of I1C to M0 and/or I0 is ±0.25 μm. Afterthe counter electrode is etched in SF₆ plasma, the wafer is anodized.

1.4 A1—Al₂O₃/Nb₂O₅ Double Layer

FIG. 4 shows the Fourth layer—A1, Anodization ring definition, A1 clearfield mask lithography defining Josephson Junctions, Ion Beam milled,chemically stripped.

The A1—Al₂O₃/Nb₂O₅ double layer is grown by anodization after RIE of thebase electrode by applying a constant voltage of about 28 mV and 700 mAinitial current forming a double protecting layer of Al₂O₃ and Nb₂O₅.The thickness of the bi-layer is about 560 Å±10%. After A1 definitionthe remaining bi-layer surrounds the Josephson junctions by about 0.5μm. A1 is aligned to I1C with an alignment tolerance of ±0.25 μm.

1.5 M1—Niobium Superconductor Counter Electrode of the Tri-Layer

FIG. 5 shows the fifth layer—M1, base electrode of the tri-layer. M1clear field mask lithography defining inductances and interconnects byRIE, chemically stripped.

The Niobium superconductor counter electrode of the tri-layer isdeposited by magnetron sputtering in a load locked, cryo-pumped chamberwith a base pressure of 1×10⁻⁹ T. It is grown to a thickness of 1500Å±10% and the film's sheet resistance at room temperature is1.70±0.2Ω/□. Most circuit inductances are defined in this layer bymicro-strip lines with M0 as ground plane and M2 for double groundplane. A specific inductance of 0.487±0.007 pH with a fringing factor of0.54±0.13 μm. Minimum line width 2 μm and a bias (−0.30±0.25) μm. Thealignment tolerance of M1 to M0 and/or I0 is ±0.25 μm.

1.6 R2—Molybdenum Resistor Material

FIG. 6 shows the sixth layer R2, Sputter deposited molybdenum, clearfield mask lithography defining the shunt and bias resistors of thecircuit, SF₆ plasma etched, chemically stripped.

The Molybdenum resistor material is deposited by magnetron sputtering ina load locked; cryo-pumped chamber with a base pressure of 1×10⁻⁷ Tright after the first part of the I1B1 dielectric is deposited. It isgrown to a thickness of 750 Å±10% and the film's sheet resistance atroom temperature is 1.95±0.1Ω/□ and is reduced to 1.0±0.1Ω/□ at 4.2 K.Minimum line width allowed is 2 μm and a bias (−0.2±0.25) μm. This biasis corrected on the mask. Shunt and bias resistors are defined in thislayer. The alignment tolerance of R2 to I1A is ±0.25 μm.

1.7 I1B—Interlayer Dielectric Between Tri-Layer and R2-I1B1; Tri-Layerand M2-I1B2

FIG. 7 shows the seventh layer I1B-1 and I1B-2—PECVD deposited, I1Blithography dark field mask defining vias to Junction, resistors andcontact pads, etched in CH₄+O₂ mixture, chemically stripped.

I1B1 and I1B2 are PECVD deposited SiO₂ insulator of thickness 2000 Å±20%with a specific capacitance of 0.416 fF/μm²±20%. Contact to M1 and I1Ais through I1B vias with a minimum size of 2 μm and a bias (0.20±0.25)μm. The alignment tolerance of I1B to I1A is ±0.1 μm.

1.8 M2—Niobium Superconductor Material

FIG. 8 shows the Eighth layer—M2, sputter deposited niobium, clear fieldmask lithography defining M2 inductors and interconnects, SF₆ RIEetched, chemically stripped.

The Niobium superconductor material is deposited by magnetron sputteringin a load locked, cryo-pumped chamber with a base pressure of 1×10⁻⁷ T.It is grown to a thickness of 3000 Å±10% and the film's sheet resistanceat room temperature is 1.60Ω/□±10%. Minimum line width 2 μm and aminimum gap between lines of 2.5 μm and a bias of (−0.5±0.25) μm. Thealignment tolerance of M2 to I1B is ±0.25 μm. This layer is mainly usedfor wiring, as an inductor with M0 as a ground plane and M3 for doubleground plane. A specific inductance of 0.67±0.01 pH/□ and Josephsonpenetration and a fringing factor of 0.98±0.19 μm.

1.9 I2—Interlayer Dielectric Between M2 and M3

FIG. 9 shows the ninth layer I2—PECVD deposited, dark field masklithography defining vias to contact pad and M2 wiring, etched in CH₄+O₂mixture, chemically stripped.

The interlayer dielectric between M2 and M3 is PECVD deposited SiO₂insulator of thickness 5000 Å±10% with a specific capacitance of 0.08fF/μm²±20%. Contact to M2 is through I2 vias with a minimum size of 2×2μm and a bias (0.20±0.25) μm. The alignment tolerance of I2 to M2 is±0.25 μm.

1.10 M3—Niobium Superconductor Material

FIG. 10 shows the tenth layer—M3, sputter deposited niobium, clear fieldmask lithography defining M3 interconnects, SF₆ RIE etched, chemicallystripped.

The Niobium superconductor material layer is deposited by magnetronsputtering in a load locked, cryo-pumped chamber with a base pressure of1×10⁻⁷ T. It is grown to a thickness of 6000 Å±10% and the film's sheetresistance at room temperature is 0.60Ω/□±10%. Minimum line width 2 μmand a minimum gap between lines of 2.5 μm and a bias of (−0.75±0.25) μm.The alignment tolerance of M3 to I2 is ±0.5 μm. This layer is mainlyused for wiring and as an inductor with M0 as a ground plane. A specificinductance of 1.26±0.02 pH/□ and a fringing factor of 1.9±0.1 μm.

1.11 R3—Titanium/Palladium/Gold (Ti/Pl/Au) Resistor Material

FIG. 11 shows the eleventh layer—R3, Image reversal lithography usingclear field mask defining R3, electron beam evaporated Ti/Pl/Au,Lift-off, chemically cleaned.

The Titanium/Palladium/Gold (Ti/Pl/Au) resistor material is deposited byelectron beam evaporation in a cryo-pumped chamber with a base pressureof 1×10⁻⁷ T. It is grown to a thickness of (300/1000/2000 Å)±10% and thefilm's sheet resistance at room temperature is 0.23±0.05Ω/□ and isreduced to 0.15±0.05Ω/□ at 4.2 K. Minimum line width 2 μm. Contact padsare defined in this layer. The alignment tolerance of R3 to M3 is ±0.5μm.

2 Rapid Planarized Process for Layer Extension (RIPPLE)

The RIPPLE process described below represents one embodiment of the newprocess for extending prior superconducting fabrication processes.

The Acronym RIPPLE stands for:

Rapid: One deposition and CMP less (˜20% less time per layer)

Integrated: to the current standard process, by adding new wiring layersunder the ground plane of the old 4-layer Process

Planarization

Process: Modified “Caldera” process (K. Hinode, et al., Physica C412-414 (2004) 1437-1441)

Layer

Extension: Easily extendible 4+n, (n=2 has been successfullydemonstrated)

All the new superconducting metal layers labeled Mn1, Mn2, Mn3 . . . areplaced below the ground plane of the current process—M0. Theinterconnect between the layers is done through Plugs labeled In1, In2,In3 . . . . The Mnx/Inx duo is deposited at one go with a thin layer ofAluminum separating them. Although Aluminum is not superconducting at4.2 K, the sub-nanometer thickness renders it superconducting because ofthe proximity effect. Once the thin film deposition of the now threelayers (Mnx—Al—Inx) is done and the both the Plug and superconductingmetal layer are defined through a fabrication process that involves:photolithography and reactive ion etch of the Plug; wet chemical or ionbeam milling of the Aluminum; photolithography and reactive ion etch ofthe superconducting metal layer. The respective interlayer dielectricare deposited and partially planarized by photolithography followed byreactive ion etch. By design the photolithography is done in such a waythat it leaves a rim of dielectric (20 nm wide) on the perimeter of thesuperconducting metal and its plug. This insures a uniform dielectricroughness throughout enabling the next process to be patternindependent. The chemical mechanical polishing is thus patternindependent and hence very uniform across the entire wafer. Thetechnology level based on the integration level is now as follows:

1) RIPPLE-0 A process where the M0 ground plane of the legacy process isplanarized with 4 superconducting layers.

2) RIPPLE-1 A process where Mn1 to M0 layers are planarized with 5superconducting metal layers.

3) RIPPLE-2 A process where Mn2 to M0 layers are planarized with 6superconducting metal layers.

4) RIPPLE-4 A process where Mn4 to M0 layers are planarized with 8superconducting metal layers.

5) RIPPLE-6 A process where Mn6 to M0 layers are planarized with 10superconducting metal layers.

6) RIPPLE-8 A process where Mn8 to M0 layers are planarized with 12superconducting metal layers

A RIPPLE-7 process where Mn8 to M0 layers are planarized is illustratedin FIG. 13, which shows the base technology level description.

2.1 Advantages of Ripple

1) Rapid: It is estimated that it is 20% faster than a process thatwould could accomplish similar results by processing one layer at atime, for example CALDERA process. See, Fourie, Coenrad; Xizhu Peng;Takahashi, Akitomo; Yoshikawa, Nobuyuki, “Modeling and calibration ofADP process for inductance calculation with InductEx,” SuperconductiveElectronics Conference (ISEC), 2013 IEEE 14th International, vol., no.,pp. 1.3, 7-11 Jul. 2013, doi: 10.1109/ISEC.2013.6604270, expresslyincorporated herein by reference. This is because the superconductingwiring layer and the plug that connects it to the subsequent layer areprocessed in parallel.

2) Easily to implement and increase the integration level ofsuperconducting electronic circuits. All the new layers are “undergroundlayers” with no effect to the layers on the top. They are undergroundbecause they go under the M0 layer of the legacy process which is mainlyused for grounding.

3) The Chemical Mechanical polishing part of the process has beenoptimized and made easy to implement by rendering it patternindependent.

4) Easily extendible, Since they same basic process is used to defineall the underground layers, as a result it is easy to accommodatedesigns that require more layers.

5) It can be adopted to define self-aligned Josephson junctions

2.2 Ripple Process Details

2.2.1 Mnx/Inx—Superconducting Metal Layer and Plugs Deposition(Nb—Al—Nb)

This is the first step in increasing the integration level ofsuperconducting electronics circuits. The Niobium-Aluminum-Niobiumtrilayer is deposited by magnetron sputtering in a load locked,cryo-pumped chamber with a base pressure of 1×10⁻⁷ T. The Niobium metallayer are grown to a thickness of 2000 Å±10% each with a 100 Å±10%Aluminum in between. The film's sheet resistance at room temperature is0.54Ω/□±10%. Minimum line width 0.8 μm and a minimum gap between linesof 0.5 μm and a bias of (−0.20±0.20) μm. This layer can be used forwiring interconnects, passive transmission lines and inductors.

2.2.1.1 Pattern Inx (“Plugs”), Reactive Ion Etch (Al as an Etch-Stop)

FIGS. 14A and 14B show the x^(th) Superconducting metal layer extension,after the plug definition.

After deposition of the tri-layer, the first step is to pattern the Plugas illustrated in FIG. 14A, which is a 3D aerial view showing two of thedefined Plugs, while FIG. 14B is a cross-sectional view zooming into oneof the plugs. Etching of metal and dielectric is done in two ReactiveIon Etching (RIE) systems. The first one is an RIE system with fluorinebased chemistries (SF₆, CHF₃, CF₄) and the second one is aninductively-coupled plasma (ICP) etch system equipped with both flouringand chlorine-based chemistries (Cl₂, BCl₃). RIE is a preferred method ofetching as it is very anisotropic with high selectivity. For niobiumetch the most commonly used are fluorine-based plasmas, e.g., SF₆plasma. The typical etch parameter are an SF₆ gas flowing at 20 sccm ina chamber pressurized to 2 Pascal and plasma sustained with an RF powerof 45.

2.2.1.2 Al Removal (Wet Etch or Anodization/Mill)

The next step is to remove the aluminum etch stop either by means of wetetch, anodization or milling.

2.2.2 Pattern #2—Mnx, Reactive Ion Etch

FIGS. 15A and 15B show the Al wet etch, Pattern #2, Niobium metal RIE.

Then photolithography is done to define the Mnx superconducting metallayer, as illustrated in FIG. 15A, shows a 3D aerial view showing two ofthe defined Mnx metals with their respective plugs while FIG. 15B showsa cross-sectional view. The reactive ion etch is done the same manner asthe plug.

2.2.3 First Interlayer Dielectric (SiO₂) Deposition (PECVD)

FIGS. 16A and 16B show the First Interlayer dielectric (SiO2)deposition.

Then SiO₂ interlayer dielectric is a plasma enhanced chemical vapordeposition (PECVD) layer formed having a thickness equal to Mnx of 2000Å±10% with a specific capacitance of 0.24 fF/μm²±20%. The resultingprofile is illustrated in FIG. 16A.

2.2.3.1 Pattern #2 (with 0.2-μm Bias) SiO₂ Planarization (RIE)

FIGS. 17A and 17B show the removal of Interlayer dielectric by ReactiveIon Etch.

The respective interlayer dielectric are deposited and partiallyplanarized by photolithography followed by reactive ion etch. By designthe photolithography is done in such a way that it leaves a rim ofdielectric (20 nm wide) on the perimeter of the superconducting metaland its plug. All dielectric layers are etched in a CHF₃ and O₂ plasma,8 sccm of O₂ and 45 sccm of CHF₃ is flown into the chamber held at apressure of 13.33 Pa. Etching is done at 150 W RF power and thetemperature on the back of the wafer is kept controlled by a chiller setto about 11° C. The resulting cross section is shown in FIG. 17A.

2.2.4 SiO₂ Deposition (PECVD)

FIGS. 18A and 18B show the Second ILD deposition.

Then SiO₂ interlayer dielectric is plasma enhance chemical vapordeposited (PECVD) thickness equal to Inx of 2000 Å±10% with a specificcapacitance of 0.24 fF/μm²±20%. The resulting profile is illustrated inFIG. 18A.

2.2.4.1 Pattern #1 (with 0.2-μm Bias), SiO₂ Planarization (RIE)

FIGS. 19A and 19B show the ILD (interlayer dielectric) Planarization byRIE SiO₂ etch.

Then photolithography is done in the same manner as pattern #1, thereactive ion etch is done in the same manner as the pattern #1,resulting in features illustrated in FIG. 19A, which shows a 3D aerialview with two of the defined Mnx metals and their respective plugs whileFIG. 19B shows a cross-sectional view.

2.2.5 SiO₂ Planarization (CMP)

FIGS. 20A and 20B show Chemical Mechanical Polishing Planarization. Thefinal, but not the least step is one that takes care of the residualinterlayer dielectric on the perimeter of the metals and the plugs bychemical mechanical polishing, resulting in a structure illustrated inFIGS. 21A and 21B, which w an alternative approach to ChemicalMechanical Polishing Planarization as shown in FIGS. 20A and 20B, ofachieving the same planarized metal with a plug, but the only differencebeing the aluminum layer that is used as an etch stop is not removedinstead is anodized and kept as part of the interlayer dielectric.

FIG. 22 shows a prior art 4-layer metal process, which is notplanarized, and thus has a varying topography between each layer.

FIG. 23 shows a planarized 6 metal layer process, in which lowerinterconnection layers have planarized topography, while the upperlayers above the ground plane (magnetic shielding layer betweeninterconnect layers and Josephson junction trilayer) are non-planar.

FIG. 24 shows a RIPPLE-8 process integrated circuit device having 12superconducting layers (8 planarized and 4 non-planarized), shieldedpassive transmission lines, and shielded DC power distributions belowthe ground plane, and 4-layer traditional non-planarized activesuperconducting circuitry above the ground plane.

FIG. 25A shows a simplified picture of a completed planarized conductinglayer and insulating overlayer, with the patterned wiring and vialabeled. A planarized intermediate structure according to the prior artis shown in FIG. 25B. According to the prior art, two planarizationsteps (produced by, e.g., CMP) are therefore required to produce FIG.25A. In contrast, in the RIPPLE process as described, the intermediatestructure of FIG. 25B is never present, but a final structure that isfunctionally equivalent to FIG. 25A is obtained using only a singleplanarization step (produced by CMP). This corresponds to a fabricationprocess that is faster and more reliable.

3. Alternative Embodiment of RIPPLE Process

The RIPPLE process above starts with deposition of a Nb/Al/Nb trilayer,where the Al act as an etch stop. This, of course, requires later stepsfor the removal of this etch stop layer. An alternative embodiment ofthe process is also presented in FIGS. 26A, 26B, and 26C, without theneed for such an etch stop or associated Al removal. The process startswith the deposition of a single 200 nm niobium thin film followed by viaplugs patterning and definition (FIG. 26A). The next step is to deposita second 200-nm thick niobium film by sputtering (FIG. 26B). During thisstep, the via-plugs will get coated conformally and grow together withthe wiring layer. At this stage, the wiring layer is patterned anddefined; the resulting structure is shown in FIG. 26C. Then 200 nmsilicon dioxide (the same thickness as the wiring layer) is deposited,yielding the same structure as shown in FIGS. 16A and 16B, except forthe aluminum. The rest of the process follows the RIPPLE steps describedwith respect to FIGS. 17-20. In this case also, only a single CMP stepis needed for each wiring layer, including the via plug. Thisalternative embodiment may provide improved reliability and speed byskipping the aluminum etch step.

These are representative examples of the RIPPLE process, and others arealso possible. The key is to pattern the vias before the wiring, whichrequires only a single CMP step for each wiring bi-layer in a processthat can be extended to an arbitrary number of such bi-layers with smallstacked vias between them.

The above description of illustrated embodiments is not intended to beexhaustive or to limit the embodiments to the precise forms disclosed.Although specific embodiments and examples are described herein forillustrative purposes, various equivalent modifications can be madewithout departing from the spirit and scope of the disclosure, as willbe recognized by those skilled in the relevant art. The teachingsprovided herein of the various embodiments can be applied to otherelectronic systems, methods and apparatus, not necessarily the exemplaryelectronic systems, methods and apparatus generally described above.

As will be apparent to those skilled in the art, the various embodimentsdescribed above can be combined to provide further embodiments. Aspectsof the present systems, methods and apparatus can be modified, ifnecessary, to employ systems, methods, apparatus and concepts of thevarious patents, applications and publications to provide yet furtherembodiments of the invention. For example, the various systems, methodsand apparatus may include a different number of metal or dielectriclayers than set out in the illustrated embodiments, such as three ormore metal layers and two or more insulating dielectric layersalternating with the metal layers, the layers may be disposed in adifferent order or area, or the embodiments may omit some elements,and/or employ additional elements.

All of the U.S. patents, U.S. patent application publications, U.S.patent applications, referred to in this specification are incorporatedherein by reference, in their entirety and for all purposes. Aspects ofthe embodiments can be modified, if necessary, to employ systems,circuits and concepts of the various patents, applications andpublications to provide yet further embodiments.

These and other changes can be made to the present systems, methods andapparatus in light of the above description. In general, in thefollowing claims, the terms used should not be construed to limit theinvention to the specific embodiments disclosed in the specification andthe claims, but should be construed to include all possible embodimentsalong with the full scope of equivalents to which such claims areentitled. Accordingly, the invention is not limited by the disclosure,but instead its scope is to be determined entirely by the followingclaims.

What is claimed is:
 1. A planarized integrated circuit on a substrate,comprising: a series of planarized layers comprising at least twolayers, formed successively on the substrate, each respective layercomprising: an electrically conductive via layer, patterned into a setof vias which define a set of vertically extending structures whichelectrically interconnect with conductive structures of an adjacentlayer; an electrically conductive layer, formed by deposition over, andadjacent to, the electrically conductive via layer patterned into theset of vias, the electrically conductive layer-being patterned into aset of wires by removal of portions of the electrically conductive layersurrounding the set of wires, with the set of vertically extendingstructures extending above the set of wires which do not overly the setof vias; a first insulating layer formed over the electricallyconductive via layer and the electrically conductive layer which isetched using an anisotropic etch process, to maintain a nonplanar raisedCaldera pattern surrounding edges of the set of wires; and a secondinsulating layer formed over the set of wires and the set of vias,formed over the first insulating layer having the maintained raisedCaldera pattern surrounding edges of the set of wires, to produce aconformal coating, which is etched using an anisotropic etch process, tomaintain conformally coated raised Caldera pattern surrounding edges ofthe set of wires, and raised Caldera pattern surrounding edges of theset of vias, the second insulating layer being planarized to exposeupper portions of the set of vertically extending structures, and removethe conformally coated raised Caldera pattern surrounding edges of theset of wires and the raised Caldera pattern surrounding edges of the setof vias, wherein the conformally coated raised Caldera pattern isindependent of the set of vertically extending structures, wherein theelectrically conductive layer, electrically conductive via layer, firstinsulating layer and second planarized insulating layer being formed asa four layer stack which is planarized once, such that upper portions ofthe set of vertically extending structures are exposed through theplanarized second insulating layer, and wherein the electricallyconductive via layer of a respective planarized layer is formed overexposed upper portions of the set of vertically extending structures ofa respectively lower planarized layer.
 2. The integrated circuit ofclaim 1, wherein at least one of the electrically conductive layer andthe electrically conductive via layer comprises a niobium-basedsuperconductive material.
 3. The integrated circuit of claim 1, whereinthe insulating layer comprises silicon dioxide.
 4. The integratedcircuit of claim 1, further comprising at least one non-planarizedcircuit layer lying above at least one planarized layer.
 5. Theintegrated circuit of claim 1, further comprising at least one Josephsonjunction formed within a planarized layer, electrically connected to theset of wires.
 6. The integrated circuit of claim 1, further comprising asingle-flux-quantum circuit formed having a Josephson junction within aplanarized layer, electrically connected to the set of wires.
 7. Theintegrated circuit of claim 1, wherein a minimum transverse dimension ofa conductive wire is less than 1 micron.
 8. The integrated circuit ofclaim 1, wherein at least one conductive layer comprises a ground plane.9. The superconducting integrated circuit of claim 1, wherein at least10 planarized layers are present.
 10. The planarized integrated circuitof claim 1, wherein the raised Caldera pattern surrounding edges of theset of vias is formed by a complementary-to-the-metal-mask pattern maskbiased for misalignment compensation, and reactive ion etching.
 11. Theplanarized integrated circuit of claim 10, wherein the electricallyconductive layer and the electrically conductive via layer are eachformed of a cryogenically superconductive material.
 12. A planarizedintegrated circuit on a substrate, comprising a series of successiveplanarized sets of layers, at least one planarized set of layerscomprising: an electrically conductive via layer patterned into a set ofvias having via edges, formed on a planar surface; a patternedelectrically conductive layer formed into a set of wires having wireedges, superposed on the patterned electrically conductive via layer,wherein portions where the set of wires which coincide in a plane of theplanarized set of layers with the set of vias, define verticallyextending conductive structures configured to provide a conductive pathbetween the set of wires of the respective layer and a set of wires ofan adjacent layer; a first insulating sublayer conformally surroundingthe set of wires and the set of vias, which is anisotropically etched toproduce a raised pattern having first protrusions corresponding to thewire edges; and a second insulating sublayer, deposited over the firstinsulating sublayer, having a raised pattern comprising secondprotrusions corresponding to the first protrusions, and the set of vias,which is anisotropically etched to produce a modified raised patternhaving third protrusions corresponding to the via edges, and the secondprotrusions, the second insulating sublayer being planarized after theanisotropic etch, such that portions of the vertically extendingstructures are exposed at an upper surface of the planarized secondinsulating sublayer, and edges of the planarized second insulatingsublayer around the exposed portions of the vertically extendingstructures, comprise planarized Caldera edges, and portions of the setof wires not superposed on the set of vias are covered by the firstinsulating sublayer and the second insulating sublayer.
 13. Theplanarized integrated circuit of claim 12, wherein the electricallyconductive via layer of a subsequent planarized set of layers isdisposed on a planarized surface of a respective planarized secondinsulating sublayer of a preceding set of layers, formed byplasma-enhanced, chemical vapor deposition, in electrical contact withthe exposed portions of the vertically extending structures of thepreceding planarized set of layers.
 14. The planarized integratedcircuit of claim 12, wherein the planarized second insulating sublayerhas a chemical-mechanical polishing planarized surface.
 15. Theplanarized integrated circuit of claim 12, comprising at least 8successive planarized sets of layers.
 16. The planarized integratedcircuit of claim 12, wherein at least one of the electrically conductivelayer, and the electrically conductive via layer is a sputtered layer.17. The planarized integrated circuit of claim 12, wherein at least oneof the electrically conductive layer and the electrically conductive vialayer has a reactive ion etching-formed pattern.
 18. The planarizedintegrated circuit of claim 12, further comprising at least oneJosephson junction formed within a planarized set of layers,electrically connected to the set of wires.
 19. The planarizedintegrated circuit of claim 12, wherein the raised pattern having firstprotrusions is formed by a complementary-to-the-metal-mask pattern maskbiased for misalignment compensation, and reactive ion etching.
 20. Theplanarized integrated circuit of claim 19, wherein the electricallyconductive layer and the electrically conductive via layer are eachformed of a cryogenically superconductive material, without anyintervening layer.
 21. A planarized integrated circuit having asubstrate, comprising at least one planarized layer formed on thesubstrate, the at least one planarized layer comprising: at least twolayers of cryogenically superconductive material formed on a planarsurface, comprising a wiring layer patterned to provide lateralconductive pathways in a plane of a respective layer, and a via layerpatterned to provide vertically conductive pathways to an overlyinglayer, wherein the via layer of a respective planarized layer ispatterned prior to superposition of the wiring layer of the respectiveplanarized layer, such that a respective via of the respectiveplanarized layer comprises a stack of the electrically conductive vialayer and the superposed electrically conductive layer having a heightabove a surrounding portion of the wiring layer; and an insulating layerformed over the at least two layers of cryogenically superconductivematerial, comprising a first non-planarized, anisotropically etched,insulating sublayer covering the wiring layer and having a pattern ofvertical protrusions corresponding to edges of the wiring layer, and asecond anisotropically etched planarized insulating sublayer formed overthe first non-planarized insulating layer, which is planarized to exposean upper portion of the stacks of electrically conductive via layer andthe electrically conductive layer, and wherein an edge of the insulatinglayer surrounding the exposed upper portion of the stacks ofelectrically conductive via layer comprise planarized Caldera edges. 22.The planarized integrated circuit according to claim 21, wherein theelectrically conductive via layer and the electrically conductive layerare each formed of a cryogenically superconducting material, without anylayer therebetween, the integrated circuit further comprising a leasttwo Josephson junctions electrically communicating through at least onewiring layer.
 23. The planarized integrated circuit of claim 21,comprising at least 8 successive planarized layers.